Refresh circuit and memory
Abstract:
A refresh circuit includes signal selector configured to select one of normal and redundant word line logical addresses as output, output signal of which is designated as first logical address; row address latch connected to output terminal of signal selector and configured to output row hammer address and row hammer flag signal according to first logical address; seed arithmetic unit connected to output terminal of row address latch and configured to generate seed address according to row hammer address; logical arithmetic unit connected to output terminal of seed arithmetic unit and configured to obtain row hammer refresh address according to seed address, row hammer refresh address is adjacent physical address of seed address; and pre-decode unit connected to output terminal of logical arithmetic unit and configured to receive row hammer refresh address, and convert it into physical address to be used by memory array of memory to perform refresh operation.
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