Invention Grant
- Patent Title: Memory system with dynamic calibration using a trim management mechanism
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Application No.: US17504467Application Date: 2021-10-18
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Publication No.: US11721399B2Publication Date: 2023-08-08
- Inventor: Michael Sheperek , Larry J. Koudele , Steve Kientz
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G11C16/26 ; G11C11/56 ; G11C16/04

Abstract:
A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trip, wherein the optimization data is managed based on iteratively calibrating the read levels and removing the calibrated levels from the optimization target data.
Public/Granted literature
- US20220036957A1 MEMORY SYSTEM WITH DYNAMIC CALIBRATION USING A TRIM MANAGEMENT MECHANISM Public/Granted day:2022-02-03
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