Invention Grant
- Patent Title: Stress compensation for wafer to wafer bonding
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Application No.: US16356402Application Date: 2019-03-18
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Publication No.: US11721554B2Publication Date: 2023-08-08
- Inventor: Anant Jahagirdar , Chytra Pawashe , Aaron Lilak , Myra McDonnell , Brennen Mueller , Mauro Kobrinsky
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt. P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/10 ; H01L29/66 ; H01L29/161 ; H01L21/20 ; H01L21/56 ; H01L21/02 ; H01L21/603
Abstract:
Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200303191A1 STRESS COMPENSATION FOR WAFER TO WAFER BONDING Public/Granted day:2020-09-24
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