Invention Grant
- Patent Title: Semiconductor device
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Application No.: US17514566Application Date: 2021-10-29
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Publication No.: US11721633B2Publication Date: 2023-08-08
- Inventor: Masaki Takahashi , Kousuke Komatsu , Rikihiro Maruyama
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki
- Agency: Rabin & Berdo, P.C.
- Priority: JP 20218274 2020.12.28
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/07 ; H01L25/18 ; H02M7/00 ; H02M7/06 ; H01L23/053 ; H02M7/5387

Abstract:
A circuit pattern, which is a second negative electrode wiring, and a horizontally extending area of a circuit pattern, which is a first negative electrode wiring, are connected electrically and mechanically by a vertically extending area of the circuit pattern and wires, which are an inter-negative-electrode wiring. As a result, N terminals and N1 terminals are equal in potential in a semiconductor device. The N terminals of a converter circuit section and the N1 terminals of an inverter circuit section are electrically connected to make the N terminals and the N1 terminals equal in potential.
Public/Granted literature
- US20220208685A1 SEMICONDUCTOR DEVICE Public/Granted day:2022-06-30
Information query
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