Invention Grant
- Patent Title: Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features
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Application No.: US16995401Application Date: 2020-08-17
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Publication No.: US11721746B2Publication Date: 2023-08-08
- Inventor: Che-Cheng Chang , Jr-Jung Lin , Shih-Hao Chen , Chih-Han Lin , Mu-Tsang Lin , Yung Jung Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/762 ; H01L29/78 ; H01L21/311
Abstract:
A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.
Public/Granted literature
- US20200381532A1 Method and Structure for FinFET Comprising Patterned Oxide and Dielectric Layer Under Spacer Features Public/Granted day:2020-12-03
Information query
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