Invention Grant
- Patent Title: Method of fabricating a transistor
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Application No.: US17362917Application Date: 2021-06-29
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Publication No.: US11721753B2Publication Date: 2023-08-08
- Inventor: Alexey Kudymov , Linlin Liu , Xiaohui Wang , Jamal Ramdani
- Applicant: POWER INTEGRATIONS, INC.
- Applicant Address: US CA San Jose
- Assignee: POWER INTEGRATIONS, INC.
- Current Assignee: POWER INTEGRATIONS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Power Integrations, Inc.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/778 ; H01L29/205 ; H01L23/31 ; H01L29/40 ; H01L23/29 ; H01L29/417 ; H01L21/3213 ; H01L29/66 ; H01L29/20 ; H01L21/02 ; H01L29/51

Abstract:
An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.
Public/Granted literature
- US20220013660A1 PROTECTIVE INSULATOR FOR HFET DEVICES Public/Granted day:2022-01-13
Information query
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