Invention Grant
- Patent Title: Method for forming gate metal structure having portions with different heights
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Application No.: US17811588Application Date: 2022-07-11
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Publication No.: US11721759B2Publication Date: 2023-08-08
- Inventor: Yu-Ping Chen , Jhen-Yu Tsai
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- The original application number of the division: US17168148 2021.02.04
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/417 ; H01L29/423

Abstract:
A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.
Public/Granted literature
- US20220344507A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2022-10-27
Information query
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