Invention Grant
- Patent Title: Vertical solid-state devices
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Application No.: US17504983Application Date: 2021-10-19
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Publication No.: US11721797B2Publication Date: 2023-08-08
- Inventor: Gholamreza Chaji
- Applicant: VueReal Inc.
- Applicant Address: CA Waterloo
- Assignee: VueReal Inc.
- Current Assignee: VueReal Inc.
- Current Assignee Address: CA Waterloo
- Agency: Nixon Peabody LLP
- Priority: CA 2986412 2017.11.14 CA 2987165 2017.11.30
- The original application number of the division: US15942154 2018.03.30
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L33/62 ; H01L33/00 ; H01L25/075 ; H01L25/16 ; H01L27/15 ; H01L33/06 ; H01L33/32 ; H01L33/50

Abstract:
As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.
Public/Granted literature
- US20220037573A1 VERTICAL SOLID-STATE DEVICES Public/Granted day:2022-02-03
Information query
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