Invention Grant
- Patent Title: Protection circuit
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Application No.: US17446599Application Date: 2021-08-31
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Publication No.: US11722102B2Publication Date: 2023-08-08
- Inventor: Tetsuro Itakura , Shuhei Miwa
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
- Priority: JP 20155724 2020.09.16
- Main IPC: H03F1/52
- IPC: H03F1/52 ; H03F3/21

Abstract:
A protection circuit comprises a first transistor, a comparator, a second transistor, and a third transistor. The first transistor has a gate connected to an input terminal and configured to pass a drain current based on a potential at the input terminal. The comparator has a non-inverting terminal to which a source of the first transistor is connected and an inverting terminal to which a reference voltage is applied. The second transistor has a gate to which an output of the comparator is applied, a source connected to a power supply voltage, and a drain connected to the input terminal. The third transistor has a gate to which a predetermined voltage is applied, a drain connected to the gate of the second transistor, and a source connected to the drain of the input transistor.
Public/Granted literature
- US20220085769A1 PROTECTION CIRCUIT Public/Granted day:2022-03-17
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