Invention Grant
- Patent Title: Resistive PCB traces for improved stability
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Application No.: US17158164Application Date: 2021-01-26
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Publication No.: US11723149B2Publication Date: 2023-08-08
- Inventor: Stephen Pardoe
- Applicant: Kioxia Corporation
- Applicant Address: JP Minato
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Allen & Overy LLP
- Main IPC: H05K1/16
- IPC: H05K1/16 ; H05K1/11 ; H05K3/04 ; H05K3/40

Abstract:
A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.
Public/Granted literature
- US20210153353A1 RESISTIVE PCB TRACES FOR IMPROVED STABILITY Public/Granted day:2021-05-20
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