The present application relates to a capacitor structure and a method for manufacturing the same, and a memory using the capacitor structure. The method includes the following operations: a substrate is provided; a stacked structure is formed on the substrate, the stacked structure including at least two support material layers arranged at an interval and a sacrificial material layer located between adjacent support material layers; capacitance holes is formed in the stacked structure, each of the capacitance holes including at least three through holes arranged in isolation; a lower electrode is formed, the lower electrode at least covering a side wall and a bottom of each through hole; the sacrificial material layer is removed, and a capacitance dielectric layer is formed on a surface of the lower electrode; and an upper electrode is formed on a surface of the capacitance dielectric layer.