Invention Grant
- Patent Title: High selectivity isolation structure for improving effectiveness of 3D memory fabrication
-
Application No.: US17333300Application Date: 2021-05-28
-
Publication No.: US11723210B2Publication Date: 2023-08-08
- Inventor: Tsu Ching Yang , Feng-Cheng Yang , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , Hung-Chang Sun , Chen-Jun Wu , Chung-Te Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H10B51/20
- IPC: H10B51/20 ; H10B51/30

Abstract:
In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.
Public/Granted literature
- US20220285395A1 HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION Public/Granted day:2022-09-08
Information query