Invention Grant
- Patent Title: Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors
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Application No.: US17502210Application Date: 2021-10-15
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Publication No.: US11742246B2Publication Date: 2023-08-29
- Inventor: Ruilong Xie , Hemanth Jagannathan , Christopher J. Waskiewicz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Thomas S. Grzesik
- The original application number of the division: US16528748 2019.08.01
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/78 ; H01L29/66 ; H01L21/762
Abstract:
A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.
Public/Granted literature
- US20220037210A1 LOCAL ISOLATION OF SOURCE/DRAIN FOR REDUCING PARASITIC CAPACITANCE IN VERTICAL FIELD EFFECT TRANSISTORS Public/Granted day:2022-02-03
Information query
IPC分类:
