- Patent Title: Barrier stacks for printed and/or thin film electronics, methods of manufacturing the same, and method of controlling a threshold voltage of a thin film transistor
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Application No.: US16659871Application Date: 2019-10-22
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Publication No.: US11742363B2Publication Date: 2023-08-29
- Inventor: Raghav Sreenivasan , Aditi Chandra , Yoocharn Jeon
- Applicant: Ensurge Micropower ASA
- Applicant Address: US CA San Jose
- Assignee: Ensurge Micropower ASA
- Current Assignee: Ensurge Micropower ASA
- Current Assignee Address: NO Oslo
- Agency: Central California IP Group, P.C.
- Agent Andrew D. Fortney
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/311

Abstract:
The present disclosure pertains to a barrier stack for thin film and/or printed electronics on substrates having a diffusible element and/or species, methods of manufacturing the same, and methods of inhibiting or preventing diffusion of a diffusible element or species in a substrate using the same. The barrier stack includes a first barrier layer on the substrate, an insulator layer on the first barrier layer, a second barrier layer on the insulator layer in a first region of the substrate, and a third barrier layer on the insulator layer in a second region of the substrate and on the second barrier layer in the first region. Each of the second and third barrier layers has a thickness less than that of the first barrier layer.
Information query
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