Invention Grant
- Patent Title: Method of converting a serial vector format (SVF) file to a vector compatible with a semiconductor testing system
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Application No.: US17869186Application Date: 2022-07-20
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Publication No.: US11747400B2Publication Date: 2023-09-05
- Inventor: Daniel M. Dosado
- Applicant: The United States of America, as represented by the Secretary of the Navy
- Applicant Address: US IN Crane
- Assignee: The United States of America, as Represented by the Secretary of the Navy
- Current Assignee: The United States of America, as Represented by the Secretary of the Navy
- Current Assignee Address: US DC Washington
- Agency: Naval Surface Warfare Center, Crane Division
- Agent Christopher Feigenbutz; Patrick B. Law
- Main IPC: G01R31/3185
- IPC: G01R31/3185 ; G01R31/3183

Abstract:
Provided is a method for enabling a semiconductor test system for testing field programmable gate arrays (FPGAs) to operate as a device programmer by converting a serial vector format (SVF) file containing a bitstream and converting the file to a vector compatible with the semiconductor test system. When executed on an HP93K test system, as an example, the vector generates JTAG (Joint Test Action Group) signals, which program the bitstream into a Field Programmable Gate Array (FPGA). The inventive method eliminates the need for a separate computer system that is normally required to run FPGA programming software and also eliminates the need to use FPGA vendor provided JTAG programming pods. Eliminating the need for the vendor software, a separate computer system, and programming pods reduces equipment cost, maintenance, and streamlines the electrical test, evaluation, and characterization of FPGAs.
Public/Granted literature
Information query
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