Invention Grant
- Patent Title: Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations
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Application No.: US17374149Application Date: 2021-07-13
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Publication No.: US11748101B2Publication Date: 2023-09-05
- Inventor: Abhishek Raja , Albin Pierrick Tonnerre
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: NIXON & VANDERHYE P.C.
- Main IPC: G06F9/312
- IPC: G06F9/312 ; G06F9/30 ; G06F9/38

Abstract:
In response to a single-copy-atomic load/store instruction for requesting an atomic transfer of a target block of data between the memory system and the registers, where the target block has a given size greater than a maximum data size supported for a single load/store micro-operation by a load/store data path, instruction decoding circuitry maps the single-copy-atomic load/store instruction to two or more mapped load/store micro-operations each for requesting transfer of a respective portion of the target block of data. In response to the mapped load/store micro-operations, load/store circuitry triggers issuing of a shared memory access request to the memory system to request the atomic transfer of the target block of data of said given size to or from the memory system, and triggers separate transfers of respective portions of the target block of data over the load/store data path.
Public/Granted literature
- US20230017802A1 HANDLING OF SINGLE-COPY-ATOMIC LOAD/STORE INSTRUCTION Public/Granted day:2023-01-19
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