Invention Grant
- Patent Title: Techniques for error correction at a memory device
-
Application No.: US17515033Application Date: 2021-10-29
-
Publication No.: US11748191B2Publication Date: 2023-09-05
- Inventor: Li Hua Tang , Qiao Hua Dong
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/30 ; G06F11/07

Abstract:
Methods, systems, and devices for techniques for error correction at a memory device are described. In some examples, as part of transmitting a command to access data stored at a memory device, a host device may transmit a combined error control code to the memory device that may be generated using the command and associated inversion information. The memory device may use the received combined error control code to perform an error control procedure on both the command and the inversion information. In some examples, while in a direct link error control code procedure mode, the host system may transmit a command to access data stored at the memory device. The host system may use a same pin or channel to transmit both an error control code for the command and an error control code for the associated data.
Public/Granted literature
- US20230135688A1 TECHNIQUES FOR ERROR CORRECTION AT A MEMORY DEVICE Public/Granted day:2023-05-04
Information query