A scramble and descramble hardware implementation method based on data bit width expansion. After expansion, redundant terms are eliminated, and scramble/descramble operation results within the current operation cycle and the value of the shift register after shifting are calculated at once. The present method exhibits advantageous effects with respect to the scramble and descramble polynomial defined by USB3.1 and PCI-Express3.0 protocols, and can obtain a relatively small hardware delay, so that the system can work at a higher frequency.