Invention Grant
- Patent Title: System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
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Application No.: US17239693Application Date: 2021-04-26
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Publication No.: US11748535B2Publication Date: 2023-09-05
- Inventor: Moez Cherif , Benoit De Lescure
- Applicant: ARTERIS, INC.
- Applicant Address: US CA Campbell
- Assignee: ARTERIS, INC.
- Current Assignee: ARTERIS, INC.
- Current Assignee Address: US CA Campbell
- Agency: DANA LEGAL SERVICES
- Agent Jubin Dana
- Main IPC: G06F30/327
- IPC: G06F30/327 ; G06F30/392

Abstract:
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
Public/Granted literature
- US20220188490A1 SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP (NoC) DESCRIPTION USING INCREMENTAL TOPOLOGY SYNTHESIS Public/Granted day:2022-06-16
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