Invention Grant
- Patent Title: Systems and methods for integrated circuit layout
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Application No.: US16746029Application Date: 2020-01-17
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Publication No.: US11748542B2Publication Date: 2023-09-05
- Inventor: Sheng-Hsiung Chen , Chun-Chen Chen , Shao-huan Wang , Kuo-Nan Yang , Chung-Hsing Wang , Ren-Zheng Liao , Meng-Xiang Lee
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsinchu
- Agency: FOLEY & LARDNER LLP
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/327 ; G06F30/3312 ; G06F30/367 ; G06F30/398 ; G06F111/04 ; G06F119/06 ; G06F119/12 ; G06F117/12

Abstract:
An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.
Public/Granted literature
- US20210224456A1 SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT Public/Granted day:2021-07-22
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