Invention Grant
- Patent Title: Super-tiling in neural network processing to enable analytics at lower memory speed
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Application No.: US16797871Application Date: 2020-02-21
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Publication No.: US11748599B2Publication Date: 2023-09-05
- Inventor: Kumar Desappan , Mihir Narendra Mody , Pramod Kumar Swami , Anshu Jain , Rishabh Garg
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Priority: IN 1941006834 2019.02.21
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06N3/063 ; G06T1/60 ; G06F12/0804 ; G06N3/08

Abstract:
Techniques including receiving a first set of values for processing by a machine learning (ML) network, storing a first portion of the first set of values in an on-chip memory, processing the first portion of the first set of values in a first layer of the ML network to generate a second portion of a second set of values, overwriting the stored first portion with the generated second portion, processing the second portion in a second layer of the ML network to generate a third portion of a third set of values, storing the third portion, repeating the steps of storing the first portion, processing the first portion, overwriting the stored first portion, processing the second portion, and storing the third portion for a fourth portion of the first set of values until all portions of the first set of values are processed to generate the third set of values.
Public/Granted literature
- US20200272892A1 SUPER-TILING IN NEURAL NETWORK PROCESSING TO ENABLING ANALYTICS AT LOWER MEMORY SPEED Public/Granted day:2020-08-27
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