The present disclosure relates to a memory device comprising:



an array of memory cells;
a plurality of boundary cells able to manage serial and parallel data;
mixed pads connected to the memory cells through low speed paths, the mixed pads being configured to be contacted by probes of a testing machine;
high speed pads connected to the boundary cells through high speed paths;
a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto at least a first input signal and a second input signal, the three state multiplexer block being also connected to the mixed pads;
ESD networks connected to the mixed pads;
an enabling circuit connected to one of the mixed pads, configured to receive an external enabling signal and to provide the three state MUX with an internal enabling signal;

wherein the enabling circuit comprises:

a tester presence detector circuit connected to the mixed pad; and
a logical gate having respective input terminals connected to the tester presence detector circuit and configured to receive the external enabling signal, and an output terminal configured to provide the internal enabling signal,

the tester presence detector circuit configured to provide a presence signal to the logical gate when a testing machine is connected to the mixed pad.





The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device, namely as embedded device as well as to a method implementing an enhanced ESD protection and a secure access to memory cells.