Ferroelectric memory arrays with reduced current leakage is described herein. A ferroelectric memory array may include a number of memory cells including capacitors with ferroelectric material. Providing an intermediary word line voltage to non-selected word lines that are not electrically coupled to a target memory cell during a sensing operation may reduce leakage current from an active data line electrically coupled to the target memory cell to the non-selected word lines. The intermediary word line voltage may be provided using an amplitude between an idle voltage of the data lines and zero volts. The intermediary word line voltage may be reduced closer to zero volts for performing a programming operation.