Invention Grant
- Patent Title: Memory management device, system and method
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Application No.: US17578086Application Date: 2022-01-18
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Publication No.: US11749343B2Publication Date: 2023-09-05
- Inventor: Nitin Chawla , Tanmoy Roy , Anuj Grover
- Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Agency: SEED INTELLECTUAL PROPERTY LAW GROUP LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G06F9/50 ; G11C29/00 ; G11C29/26 ; G11C29/44 ; G06N3/063

Abstract:
A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.
Public/Granted literature
- US20220139453A1 MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD Public/Granted day:2022-05-05
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