Invention Grant
- Patent Title: Method of testing a memory circuit and memory circuit
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Application No.: US17198898Application Date: 2021-03-11
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Publication No.: US11749370B2Publication Date: 2023-09-05
- Inventor: Chao-I Wu , Shih-Lien Linus Lu , Sai-Hooi Yeong
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G11C29/38
- IPC: G11C29/38 ; G11C16/08 ; G06F11/20 ; G11C16/26 ; G11C16/10

Abstract:
A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.
Public/Granted literature
- US20210375381A1 METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUIT Public/Granted day:2021-12-02
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