Invention Grant
- Patent Title: Method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing
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Application No.: US17233867Application Date: 2021-04-19
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Publication No.: US11749533B2Publication Date: 2023-09-05
- Inventor: Steffen Ziesche , Christian Lenz , Uwe Waltrich , Christoph Bayer , Hoang Linh Bach , Andreas Schletz
- Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E. V.
- Applicant Address: DE Munich
- Assignee: Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V.
- Current Assignee: Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V.
- Current Assignee Address: DE Munich
- Agency: Leydig, Voit & Mayer, Ltd.
- Priority: DE 2020205043.0 2020.04.21
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/373 ; H01L23/367 ; H01L21/52

Abstract:
Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.
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