Invention Grant
- Patent Title: Techniques for void-free material depositions
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Application No.: US17028259Application Date: 2020-09-22
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Publication No.: US11749564B2Publication Date: 2023-09-05
- Inventor: M. Arif Zeeshan , Kelvin Chan , Shantanu Kallakuri , Sony Varghese , John Hautala
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDW Firm PLLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/48

Abstract:
Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.
Public/Granted literature
- US20220093458A1 TECHNIQUES FOR VOID-FREE MATERIAL DEPOSITIONS Public/Granted day:2022-03-24
Information query
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