A vertically alternating sequence of unit layer stacks is formed over a substrate. Each unit layer stacks includes an insulating layer and a spacer material layer that is formed as, or is subsequently replaced with, a first electrically conductive layer. A 2×N array of stepped surfaces is formed. Each column of two stepped surfaces other than one column is vertically extended by performing a set of processing sequences at least once. The set of processing sequences includes forming a patterned etch mask layer and etching an unmasked subset of the 2×N array. One or more patterned etch mask layer has a respective continuous opening including an entire area of a respective 2×M array of stepped surfaces that is a subset of the 2×N array of stepped surfaces. Vertical stacks of memory elements are formed through the vertically alternating sequence.