Invention Grant
- Patent Title: Die-substrate assemblies having sinter-bonded backside via structures and associated fabrication methods
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Application No.: US17500318Application Date: 2021-10-13
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Publication No.: US11749639B2Publication Date: 2023-09-05
- Inventor: Lakshminarayan Viswanathan , Jaynal A. Molla
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L21/786
- IPC: H01L21/786 ; H01L23/00 ; H01L21/768 ; H01L23/48

Abstract:
Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.
Public/Granted literature
- US20230111320A1 DIE-SUBSTRATE ASSEMBLIES HAVING SINTER-BONDED BACKSIDE VIA STRUCTURES AND ASSOCIATED FABRICATION METHODS Public/Granted day:2023-04-13
Information query
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