Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US17378790Application Date: 2021-07-19
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Publication No.: US11749651B2Publication Date: 2023-09-05
- Inventor: Jie Chen , Hsien-Wei Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/07
- IPC: H01L25/07 ; H01L23/00 ; H01L23/31 ; H01L23/538 ; H01L25/00

Abstract:
A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.
Public/Granted literature
- US20210343681A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-11-04
Information query
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