A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents based on the reference current, a plurality of inverters, and a Schmitt trigger configured to generate an output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a period (TCHARGE) correlated with TDEL. Some inverters and the Schmitt trigger are configured to be current starved when the input clock signal is high and are configured to be shorted to ground and the reference current when the input clock signal is low. TDEL is based on TCHARGE and TCHARGE is based on C, NTOP, VST,High, and a supply voltage.