- Patent Title: Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same
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Application No.: US17176903Application Date: 2021-02-16
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Publication No.: US11750225B2Publication Date: 2023-09-05
- Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim , Jae-Young Lee , Nam-Ho Hur
- Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Applicant Address: KR Daejeon
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon
- Priority: KR 20150023409 2015.02.16
- Main IPC: H03M13/27
- IPC: H03M13/27 ; H03M13/11 ; H03M13/25 ; H03M13/53 ; H03M13/00

Abstract:
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
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