Invention Grant
- Patent Title: Multi-rate ECC parity for fast SLC read
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Application No.: US17331346Application Date: 2021-05-26
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Publication No.: US11755407B2Publication Date: 2023-09-12
- Inventor: Dudy David Avraham , Ran Zamir , Eran Sharon
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: PATTERSON + SHERIDAN, LLP
- Agent Steven H. VerSteeg
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/09 ; H03M13/11

Abstract:
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.
Public/Granted literature
- US20220385303A1 Multi-Rate ECC Parity For Fast SLC Read Public/Granted day:2022-12-01
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