Invention Grant
- Patent Title: Storing a logical-to-physical mapping in NAND memory
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Application No.: US17202983Application Date: 2021-03-16
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Publication No.: US11755495B2Publication Date: 2023-09-12
- Inventor: Sanjay Subbarao
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1009 ; G11C16/04 ; G06F12/0815 ; G11C14/00 ; G11C11/56

Abstract:
A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.
Public/Granted literature
- US20220300431A1 STORING A LOGICAL-TO-PHYSICAL MAPPING IN NAND MEMORY Public/Granted day:2022-09-22
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