Invention Grant
- Patent Title: Methods of forming transistors having raised extension regions
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Application No.: US17685448Application Date: 2022-03-03
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Publication No.: US11756624B2Publication Date: 2023-09-12
- Inventor: Haitao Liu
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- The original application number of the division: US16451143 2019.06.25
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H10B41/35 ; H10B43/35 ; G11C5/06 ; H10B41/27 ; H10B41/41 ; H10B43/27 ; H10B43/40

Abstract:
Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type.
Public/Granted literature
- US20220189553A1 METHODS OF FORMING TRANSISTORS HAVING RAISED EXTENSION REGIONS Public/Granted day:2022-06-16
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