Invention Grant
- Patent Title: Chip integration into cavities of a host wafer using lateral dielectric material bonding
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Application No.: US18155607Application Date: 2023-01-17
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Publication No.: US11756848B1Publication Date: 2023-09-12
- Inventor: Florian Herrault , Isaac Rivera , Daniel S. Green , James F. Buckwalter
- Applicant: PseudolithIC, Inc.
- Applicant Address: US CA Santa Barbara
- Assignee: PseudolithIC, Inc.
- Current Assignee: PseudolithIC, Inc.
- Current Assignee Address: US CA Santa Barbara
- Agency: SoCal IP Law Group LLP
- Agent Angelo J. Gaz; Steven C. Sereboff
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31 ; H01L23/00
Abstract:
An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
Information query
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