Invention Grant
- Patent Title: Fan-out packaging structure and method
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Application No.: US17476340Application Date: 2021-09-15
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Publication No.: US11756871B2Publication Date: 2023-09-12
- Inventor: Yenheng Chen , Chengchung Lin
- Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Applicant Address: CN Jiangyin
- Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee Address: CN Jiangyin
- Agency: Alston & Bird LLP
- Priority: CN 2010969175.9 2020.09.15 CN 2022013581.6 2020.09.15
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L23/498 ; H01L23/00 ; H01L25/10 ; H01L21/48

Abstract:
The present disclosure provides a fan-out packaging structure and a method for fabricating the fan-out packaging. The fan-out packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first filling layer, a first packaging layer, a stacked chip package, a passive element, a second filling layer, a second packaging layer, and metal bumps. By means of the present disclosure, various chips having different functions can be integrated into one packaging structure, thereby improving the integration of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertical stacked packaging is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be significantly shortened, thereby reducing the power consumption, increasing the signal transmission speed, and increasing the data processing capacity.
Public/Granted literature
- US20220084925A1 FAN-OUT PACKAGING STRUCTURE AND METHOD Public/Granted day:2022-03-17
Information query
IPC分类: