Invention Grant
- Patent Title: Semiconductor structure and manufacturing method thereof
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Application No.: US17226081Application Date: 2021-04-09
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Publication No.: US11756920B2Publication Date: 2023-09-12
- Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Hsing-Chih Lin , Zheng-Xun Li
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/48 ; H01L23/522 ; H01L23/528 ; H01L21/768 ; H01L25/00

Abstract:
A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure. A bonding feature of the second front-side bonding structure includes a first bonding via in contact with the second interconnect structure, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.
Public/Granted literature
- US20220328447A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2022-10-13
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