Invention Grant
- Patent Title: Reducing gate resistance in stacked vertical transport field effect transistors
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Application No.: US17321563Application Date: 2021-05-17
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Publication No.: US11756957B2Publication Date: 2023-09-12
- Inventor: Heng Wu , Chen Zhang , Kangguo Cheng , Tenko Yamashita , Joshua M. Rubin
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Thomas S. Grzesik
- The original application number of the division: US16395563 2019.04.26
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/78 ; H01L21/84 ; H01L29/66

Abstract:
A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.
Public/Granted literature
- US20210280578A1 REDUCING GATE RESISTANCE IN STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS Public/Granted day:2021-09-09
Information query
IPC分类: