Invention Grant
- Patent Title: Planarization of backside emitting VCSEL and method of manufacturing the same for array application
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Application No.: US16824390Application Date: 2020-03-19
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Publication No.: US11757255B2Publication Date: 2023-09-12
- Inventor: Yi-Ching Pao
- Applicant: OEpic SEMICONDUCTORS, INC
- Applicant Address: US CA Sunnyvale
- Assignee: OEpic Semiconductors, Inc.
- Current Assignee: OEpic Semiconductors, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Weiss & Moy, PC
- Agent Jeffrey D. Moy
- The original application number of the division: US16258976 2019.01.28
- Main IPC: H01S5/183
- IPC: H01S5/183 ; H01S5/42 ; H01S5/0234 ; H01S5/042 ; H01S5/026 ; H01S5/0237 ; H01S5/02345

Abstract:
A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
Public/Granted literature
- US20200220328A1 PLANARIZATION OF BACKSIDE EMITTING VCSEL AND METHOD OF MANUFACTURING THE SAME FOR ARRAY APPLICATION Public/Granted day:2020-07-09
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