We describe techniques to reduce DC ripple voltage in an inverter by determining a plurality of switching events for each of the three phases in each Pulse Width Modulation (PWM) period. The switching events provide a desired target output voltage for the respective PWM period. From this determination of the switching events, a comparison can be made to determine a first time period between a first and second switching event across all of the phases, and a second time period between the second and a third switching event across all of the phases. The timing of one or more switching events in only one of the phases in the respective PWM period is adjusted in response to the determined time period being greater than a threshold in order to reduce the determined first or second time period.