Invention Grant
- Patent Title: Integrated circuit overlay test patterns and method thereof
-
Application No.: US17327990Application Date: 2021-05-24
-
Publication No.: US11762302B2Publication Date: 2023-09-19
- Inventor: Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US16008267 2018.06.14
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L29/78 ; G03F7/20 ; G03F9/00 ; G03F7/00

Abstract:
Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
Public/Granted literature
- US20210278771A1 Integrated Circuit Overlay Test Patterns and Method Thereof Public/Granted day:2021-09-09
Information query
IPC分类: