Invention Grant
- Patent Title: Method for protecting a reconfigurable digital integrated circuit against reversible errors
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Application No.: US17881649Application Date: 2022-08-05
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Publication No.: US11762722B2Publication Date: 2023-09-19
- Inventor: Yann Oster
- Applicant: THALES
- Applicant Address: FR Courbevoie
- Assignee: THALES
- Current Assignee: THALES
- Current Assignee Address: FR Courbevoie
- Agency: BakerHostetler
- Priority: FR 08653 2021.08.12
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G01R31/3185 ; G01R31/3187 ; G01R31/319 ; H03K19/17728 ; G06F11/16

Abstract:
A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.
Public/Granted literature
- US20230051943A1 METHOD FOR PROTECTING A RECONFIGURABLE DIGITAL INTEGRATED CIRCUIT AGAINST REVERSIBLE ERRORS Public/Granted day:2023-02-16
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