Invention Grant
- Patent Title: Method and system for custom model definition of analog defects in an integrated circuit
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Application No.: US17235605Application Date: 2021-04-20
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Publication No.: US11763056B2Publication Date: 2023-09-19
- Inventor: Mayukh Bhattacharya , Michael Durr , Mira Tzakova , Beatrice Solignac , Rayson Yam
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G06F30/367
- IPC: G06F30/367 ; G06F119/02

Abstract:
A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.
Public/Granted literature
- US20210326506A1 METHOD AND SYSTEM FOR CUSTOM MODEL DEFINITION OF ANALOG DEFECTS IN AN INTEGRATED CIRCUIT Public/Granted day:2021-10-21
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