Invention Grant
- Patent Title: Methods and apparatuses for aligning read data in a stacked semiconductor device
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Application No.: US17316140Application Date: 2021-05-10
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Publication No.: US11763855B2Publication Date: 2023-09-19
- Inventor: Seiji Narui
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C5/02
- IPC: G11C5/02 ; H01L25/065 ; G11C5/04 ; H10B99/00

Abstract:
Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.
Public/Granted literature
- US20210264955A1 METHODS AND APPARATUSES FOR ALIGNING READ DATA IN A STACKED SEMICONDUCTOR DEVICE Public/Granted day:2021-08-26
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