Invention Grant
- Patent Title: Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches
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Application No.: US16240156Application Date: 2019-01-04
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Publication No.: US11764263B2Publication Date: 2023-09-19
- Inventor: Ehren Mannebach , Anh Phan , Aaron Lilak , Willy Rachmady , Gilbert Dewey , Cheng-Ying Huang , Richard Schenker , Hui Jae Yoo , Patrick Morrow
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L27/088 ; H01L29/417 ; H01L29/66 ; H01L29/78 ; H01L29/423

Abstract:
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.
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Information query
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