Invention Grant
- Patent Title: Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
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Application No.: US17379208Application Date: 2021-07-19
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Publication No.: US11764286B2Publication Date: 2023-09-19
- Inventor: Kuo-Cheng Ching , Chih-Hao Wang , Shi Ning Ju , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US16446312 2019.06.19
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/775 ; H01L29/165 ; H01L21/8234 ; H01L21/02 ; H01L27/088
Abstract:
A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.
Public/Granted literature
- US20210351279A1 Reducing Parasitic Capacitance for Gate-All-Around Device By Forming Extra Inner Spacers Public/Granted day:2021-11-11
Information query
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