Hardware architecture for memory organization for fully homomorphic encryption
Abstract:
Systems and memory devices are disclosed for fully homomorphic encryption (FHE). The system may include a processing unit including: a data memory for storing coefficients for a polynomial; a twiddle factor (TF) memory for storing TF values associated with the polynomial; a TF register connected to the TF memory; a plurality of first registers connected to the data memory; a plurality of first MUXs connected to the first registers; a plurality of second registers connected to the plurality of first MUXs; a plurality of Butterfly (BF) cores connected to the plurality of the second registers and the TF register; wherein each of the plurality of BF cores is configured to, responsive to a control signal, perform a Butterfly Transform (BFT) operation based on two coefficients from the data memory and a TF value from the TF memory.
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