Invention Grant
- Patent Title: Three-dimensional memory device without gate line slits and method for forming the same
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Application No.: US17100874Application Date: 2020-11-21
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Publication No.: US11765897B2Publication Date: 2023-09-19
- Inventor: Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: BAYES PLLC
- Priority: CN 1910522002.X 2019.06.17
- The original application number of the division: US16670586 2019.10.31
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H10B43/10 ; H10B43/35

Abstract:
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate. The method may further include forming a first top select structure extending along the vertical direction through a top conductor layer of the plurality of conductor layers and along the horizontal direction to divide the top conductor layer into a pair of top select conductor layers. The first top select structure and the bottom select structure may be aligned along the vertical direction and may divide a plurality of memory cells formed by the plurality of conductor layers and the plurality of channel structures into a pair of memory blocks.
Public/Granted literature
- US20210104549A1 THREE-DIMENSIONAL MEMORY DEVICE WITHOUT GATE LINE SLITS AND METHOD FOR FORMING THE SAME Public/Granted day:2021-04-08
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