Invention Grant
- Patent Title: Test circuit and method
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Application No.: US18151959Application Date: 2023-01-09
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Publication No.: US11768235B2Publication Date: 2023-09-26
- Inventor: Hsieh-Hung Hsieh , Yen-Jen Chen , Tzu-Jin Yeh
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.
Public/Granted literature
- US20230160954A1 TEST CIRCUIT AND METHOD Public/Granted day:2023-05-25
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